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c-mos a/v data rec process (gate array)
- top view - CXD8989R (1/4)
il11 132
130
125
120
115
110
105
100
95
90
89 133
135
140
145
150
155
160
165
170
175
176 1
5
10
15
20
25
30
35
40
44 88
85
80
75
70
65
60
55
50
45 gnd v dd (+5 v) gnd gnd v dd (+5 v) gnd v dd (+5 v) gnd gnd v dd (+5 v) gnd gnd v dd (+5 v) gnd gnd v dd (+5 v) gnd gnd gnd gnd v dd (+5 v) gnd gnd v dd (+5 v)
CXD8989R (2/4) 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
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30
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33
34
35
36
37
38
39
40
41
42
43
44 diag
aint0
aint1
pay _ en
aint2
gnd
aden2
sw _ det
pcerd
in _ fp
rx _ init
v dd
diagre
diagrst
atriwe
atrirstw
gnd
s _ dat0
s _ dat1
s _ dat2
s _ dat3
s _ dat4
s _ dat5
s _ dat6
s _ dat7
s _ dat8
s _ dat9
gnd
wccont0
wccont1
wccont2
wccont3
v dd
wccont4
main _ we
w _ init
m _ rstw
h _ rec
gnd
gwdata0
gwdata1
gwdata2
gwdata3
gwdata4 o
i
i
i
i
? i
i
i
i
o
? o
o
o
o
? i
i
i
i
i
i
i
i
i
i
? o
o
o
o
? o
o
o
o
o
? o
o
o
o
o (v dd = +5 v) 45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88 gwdata5
gwdata6
gwdata7
gwsync
gwstart
gnd
gwend
we _ v
we _ a
we _ t
rstw _ v
v dd
rstw _ a
rstw _ t
w _ cko
w _ ck
gnd
grdata0
grdata1
grdata2
grdata3
grdata4
grdata5
grdata6
grdata7
grsync
grstart
gnd
grend
re _ v
rstr _ v
xsm
v dd
xtst
sdi
sdo
re _ a
rstr _ a
gnd
cadrs0
cadrs1
cadrs2
cadrs3
cadrs4 o
o
o
o
o
? o
o
o
o
o
? o
o
o
i
? i
i
i
i
i
i
i
i
i
i
? i
o
o
i
? i
i
o
o
o
? i
i
i
i
i 89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132 cadrs5
cadrs6
cadrs7
crd
cwr
gnd
ccs
cdata0
cdata1
cdata2
cdata3
v dd
cdata4
cdata5
cdata6
cdata7
gnd
dma _ dat0
dma _ dat1
dma _ dat2
dma _ dat3
dma _ dat4
dma _ dat5
dma _ dat6
dma _ dat7
dfwe1
dfwe2
gnd
dfwe3
dfwe4
dfrstw
dma _ dreq
v dd
rccont0
rccont1
rccont2
rccont3
rccont4
gnd
r _ dat0
r _ dat1
r _ dat2
r _ dat3
r _ dat4 i
i
i
i
i
? i
i/o
i/o
i/o
i/o
? i/o
i/o
i/o
i/o
? o
o
o
o
o
o
o
o
o
o
? o
o
o
i
? o
o
o
o
o
? i
i
i
i
i 133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176 r _ dat5
r _ dat6
r _ dat7
i _ port0
i _ port1
gnd
test _ r
pint _ re0
pint _ re1
pint _ re2
pint _ re3
v dd
pint _ re4
pint _ re5
pint _ re6
pint _ re7
gnd
w _ dat0
w _ dat1
w _ dat2
w _ dat3
w _ dat4
w _ dat5
w _ dat6
w _ dat7
o _ port0
o _ port1
gnd
main _ re
p _ init
m _ rstr
xack
v dd
bck
xtck
test _ w
wccont5
rccont5
gnd
ext _ cs0
ext _ cs1
r _ ck
sg _ fp
sys _ rst i
i
i
i
i
? o
o
o
o
o
? o
o
o
o
? o
o
o
o
o
o
o
o
o
o
? o
o
o
i
? i
i
o
o
o
? o
o
i
i
i pin
no. i/o signal pin
no. i/o signal pin
no. i/o signal pin
no. i/o signal
CXD8989R (3/4) input
aden2, pay _ en
aint0
aint1
aint2
bck, xack, xtck
cadrs0 - cadrs7
ccs
crd
cwr
dma _ dreq
grdata0 - grdata7
grend
grstart
grsync
i _ port0, i _ port1
in _ fp, sg _ fp
pcerd
r _ ck
r _ dat0 - r _ dat7
s _ dat0 - s _ dat10
sdi, xsm, xtst
sw _ det
sys _ rst
w _ ck
; data enable (sddi rx)
; video/non-av interrupt (sddi rx)
; audio interrupt (sddi rx)
; attribute interrupt (sddi rx)
; ic test pin
; cpu address bus
; cpu chip select
; cpu read pulse
; cpu write pulse
; dma fifo write request
; gop delay read data in
; gop delay end pulse
; gop delay start pulse
; gop delay sync
; in port
; frame pulse in
; payload crcc error (sddi rx)
; read process clock
; main fifo read data in
; data in (sddi rx)
; ic test pin
; switching detect (sddi rx)
; power on reset
; write process clock
CXD8989R (4/4) output
atrirstw
atriwe
dfrstw
dfwe1 - dfwe4
diag
diagre
diagrst
dma _ dat0 - dma _ dat7
ext _ cs0, ext _ cs1
gwdata0 - gwdata7
gwend
gwstart
gwsync
h _ rec
m _ rstr
m _ rstw
main _ re
main _ we
o _ port0, o _ port1
p _ init
pint _ re0 - pint _ re7
rccount0 - rccount5
re _ a
re _ v
rstr _ a
rstr _ v
rstw _ a
rstw _ t
rstw _ v
rx _ init
sdo
test _ r
test _ w
w _ cko
w _ dat0 - w _ dat7
w _ init
wccount0 - wccount5
we _ a
we _ t
we _ v
input/output
cdata0 - cdata7
; attribute fifo rstw
; attribute fifo write enable
; dma fifo rstw
; dma fifo write enable
; diag mode sel (h: diag mode)
; diag fifo read enable
; diag fifo rstr
; dma fifo write data out
; chip select out
; gop delay write data out
; gop delay end pulse out
; gop delay start pulse out
; gop delay sync out
; rec led drive (h: rec)
; main fifo rstr
; main fifo rstw
; main fifo read enable
; main fifo write enable
; out port
; main fifo power on initial pulse
; main fifo power on initial chip select
; main fifo read chip counter out
; audio fifo read enable
; video fifo read enable
; audio fifo rstr
; video fifo rstr
; audio fifo rstw
; time code fifo rstw
; video fifo rstw
; cpu interrupt
; ic test pin
; ic test
; ic test
; write process clock out
; main fifo write data out
; main fifo power on initial pulse
; main fifo write chip counter out
; audio fifo write enable
; time code fifo write enable
; video fifo write enable
; cpu data bus 0 - 7
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